Read Write Ram With Data Bus in Verilog

Nosotros have discussed quite a few times in this 8085 course well-nigh how the 8085 reads and writes data from or to memory. But nosotros know that unlike microcontrollers that have a certain amount of born retention, microprocessors do non have their own memory except for a few registers. And so, where does 8085 read and write data?

Since 8085 does not have whatever substantial internal memory, we need to attach external memory chips. How do we connect a memory chip to the 8085 and manage the interactions between the 2 chips? That is what we are going to learn in this mail service.

We will take up a problem statement and solve it pace by pace, learning the concepts in the process as we motion along.

Retentiveness support in 8085
Retention chips of different types and sizes
Retention interfacing – Problem argument
- Pin diagram of memory chips
- Connecting Control Signals
- Data Bus interfacing
- Address bus Interfacing
- Generating the chip select signal
- The final circuit

Retention back up in 8085

An 8085 microprocessor has a sixteen-flake accost jitney. Each bit tin can accept the value of either 0 or ane. So, the total number of addresses that can exist generated on a 16-bit address motorcoach will be 25 6 . And each unique address refers to a memory block containing eight bits or ane byte of space.

Thus, we can say that 8085 can support a retentivity flake of size up to 64 kB. We can interface a memory chip of size less than that also. Also, nosotros can interface several retention chips to a single 8085 microprocessor, until and unless their combined size does not exceed 64 kB. Allow us learn how to reach all that.

Memory chips of different types and sizes

Retentiveness chips come in a diverseness of types and with different storage capacities. A broad classification of retentivity fries based on their read and write capability is:

RAM (Random Admission Memory):Nosotros tin read besides as write data on this blazon of retention. The chip of this type has pins for both memory read and retention write signals.
ROM (Read Simply Memory): As the name suggests, nosotros tin but write data on this type of memory chip. The chip of this blazon has a pin only for memory read signal.

Now, y'all must be wondering what does a microprocessor read from a ROM if information cannot be written on it.

Data cannot be written on it by a microprocessor when information technology is connected in the circuit. Just data tin can be written on it using some special techniques. This kind of retentivity is used to store programs, while RAM is used to store the information.

ROM is also of ii types:

EPROM (Erasable Programmable Read-But Retentiveness): The contents of an EPROM are erased past UV rays. Information is written on it optically.
EEPROM (Electronically Erasable Programmable Read-Only Memory): As the name suggests, information is written and removed on this blazon of ROM electronically.

You can larn more about all the types of digital memories here.

Retention chips come up in different sizes. The illustration shows below what these numbers in the specification of a memory chip capacity (size) hateful.

Now, let us larn through an example, how external RAM and external ROM chips can exist interfaced with 8085. Let us take upwards a trouble regarding the interfacing of memory and solve information technology as we larn the topic.

Memory interfacing – Problem argument

Interface a 1kB EPROM and a 2 kB RAM with microprocessor 8085. The accost allotted to one kB EPROM should be 2000H to 22FFH. You can assign the accost range of your choice to the two kB RAM.

The first step to solve this trouble is to empathize the pins of the given memory fries.

Pin diagram of memory fries

RAM and ROM both have same pins, except for WR pivot, which is nowadays in RAM and is non in that location in a ROM. Let us understand the pins ane past one.

Data pins: Since each memory location stores eight bits, at that place are eight data lines D0-D7 connected to the memory flake.
Address pins: The number of address pins depends on the size of the retention. In this case, a memory of size 1 kB 10 8 will have 2¹⁰ different memory locations. Hence, information technology will have ten address lines A0 to A9. Similarly, the 2 kB RAM will accept 2^xi dissimilar memory locations. So, there are 11 address lines A0-A10.
CS pivot: When this pin is enabled, the memory flake knows that the microprocessor is talking to information technology and responds to it accordingly. We need to generate this bespeak for each of the chips according to the range of addresses assigned to them. Basically, we select a chip only when information technology is needed. The Chip Select (CS) pin is used for this.
OE pivot: When this active-low output enable pin is enabled, the retention chip can output the information into the information bus.
WR pin: Upon activation of this active-low memory write pivot, data on the data bus is written on the memory fleck at the location specified by the address bus.
VCC and GND pins: These pins serve the purpose of powering the ICs. For simplicity, we will not show these pins in the diagram.

There are three types of buses in 8085 – Address omnibus, data bus, and control passenger vehicle. Each of these buses will be connected to the memory scrap.

Connecting Control Signals

In the memory chips, at that place are two pins for control signals – OE (Output Enable) and WR (Retentiveness Write) . These volition be continued to the control signals generated using a 3 to 8 decoder. To read about the generation of control signals, y'all tin read our mail on Demultiplexing of Bus and Generating Control Signals . The circuit for generating control signals is shown below.

Four control signals are generated when we input the WR, RD and IO/M signals from the 8085 to the 3:8 decoder – IOR, IOW, MEMR and MEMW. Since we are dealing with memory, we will just demand MEMR and MEMW signals.

While reading from a retentiveness scrap, it's output should be enabled. And then, MEMR volition be connected to theOE pin. Similarly, for writing to a memory chip, MEMW will exist connected to the WR pin of the RAM. Afterwards completing these 2 connections, we are done with the control signals except CS. We volition deal with that in a chip.

Data Bus interfacing

In that location are viii lines comprising the data bus of both 8085 and the memory chips. The interfacing of the data bus is the simplest part. Nosotros just connect respective lines (D0-D7 from 8085) to the respective pins (D0-D7 of the memory chip).

Address charabanc Interfacing

We have a 2kB RAM with 11 accost lines. Then, the start eleven lines of the address omnibus of 8085 will be connected to the corresponding address lines of the 2kB RAM. Similarly, the commencement ten lines of the accost bus of 8085 will exist connected to the corresponding lines of 1kB EPROM. The remaining address lines will be used to generate the chip select (CS) signal.

Generating the scrap select signal

This is a little tricky, but it'due south the near important role of solving the problem. Permit united states of america proceed footstep by footstep and build upwardly an intuition of how to generate the chip select signal for a retention of given size and given address range.

Let u.s.a. tabulate the starting and ending address of the 1kB EPROM.

A15 is most significant, and A0 is the least significant fleck. The accost range for placing the EPROM is from 2000H to 22FFH (equally given in the question.) Translating these to binary:

2000H = 0011 0000 0000 0000

22FFH = 0011 0011 1111 1111

Accost bit number	A15	A14	A13	A12	A11	A10	A9	A8	A7	A6	A5	A4	A3	A2	A1	A0
Starting address	0	0	1	1	0	0	0	0	0	0	0	0	0	0	0	0
Ending Address	0	0	i	1	0	0	1	1	one	1	1	ane	one	1	i	1

From the in a higher place table, we can notice that ten bits from A0 to A9 are irresolute. These ten bits are straight connected to the address lines of the memory chip.

These ten bits take the value of either 0 or ane to course addresses. The start address is 00 0000 0000, and the 2nd address is 00 0000 0001, the third is 00 0000 0010 and so on. The last accost will be 11 1111 1111.

Meanwhile, $.25 A11 to A15 do not change and don't have whatsoever effect on the addressing process inside the memory chip. So, nosotros tin conclude that the values of bits A15-A11 (0011 00) given in the above table are in a unique, unchanging configuration for this memory chip. If even one of these $.25 changes, the address won't belong to this retentivity chip. And so, nosotros can employ these values of A15-A11 to uniquely identify this memory chip, which is exactly what the CS bespeak is supposed to practice.

We tin can say that when A15 = A14 = A11 = A10 = 0 and A13 = A12 = i, then our memory chip should be selected. Now, nosotros need to design the logic to generate the CS signal. The resulting Boolean equation of CS will be:

CS = Complement of (A15* . A14* . A13 . A12 . A11* . A10*)

This equation tin can be implemented using NAND Gate. The final flake select logic for 1kB EPROM is illustrated below.

At present, nosotros accept to generate a fleck select signal for the second retentiveness scrap, which is 2kB RAM. The procedure is quite like and differs from the previous i in ii means:

The size of the memory is different. So, there are 11 accost lines instead of ten.
Nosotros are not given an address range here. Nosotros are given the liberty to decide on our ain.

Like to the previous case, we connect the kickoff 11 address lines of the 8085 microprocessor to the 11 address lines of the 2kB RAM. These $.25 volition have values of 0 and i and will generate two * 1024 different addresses. The address bits A10-A0 will vary from 000 0000 0000 to 111 1111 1111.

What about the remaining address bits? Well, they don't have whatsoever role in the addressing of the memory in this 2kB RAM. So, nosotros tin can gear up them to a certain value without affecting anything. Let's fix them to 0000 0. Thus, the address range for this chip becomes 0000 0000 0000 0000 to 0000 0111 1111 1111. In hexadecimal, the accost range will be from 0000H to 07FFH.

Address bit number	A15	A14	A13	A12	A11	A10	A9	A8	A7	A6	A5	A4	A3	A2	A1	A0
Starting address	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
Ending Address	0	0	0	0	0	1	1	i	1	ane	1	1	1	1	1	1

We use a similar technique here. We use the remaining bits A15-A11 to uniquely identify this chip i.e., to generate flake select bespeak. And then, the boolean equation will be

CS = Complement of (A15* . A14* . A13* . A12* . A11*)

The implementation of this equation using NAND Gate to generate theCS signal is shown in the following image.

The last excursion

Since we now have the chip select logic and have decided all the connections, it'south time to finalize the circuit. The entire external retentiveness interfacing circuit tin exist broken up into five different parts:

8085 microprocessor
Demultiplexing of address/data bus
Generation of control signals
Generation of chip select signals
Memory chips

The images below show the final circuit with all the 5 parts listed higher up integrated into a single excursion. Just the connections are shown in the first diagram. In the diagram following it, different subsections of the circuit are labeled.

The above diagram summarizes the unabridged procedure of interfacing the external memory with the 8085 microprocessor. If you have whatever queries regarding the topic, driblet a comment below, and we will get back to y'all.

Lowery Exactionan1944